The present invention relates to a logic integrated circuit, and more particularly to a scan path circuit for testing a sequential circuit.
1. Description of the Related Art
In general, it is difficult to test a sequential circuit within a logic integrated circuit in comparison with a combinational circuit, and many design for testability methods have been carried out. Among them, a scan path method which enables direct application to flip-flops from external or direct observation of FFs has been widely used.
However in a conventional scan path circuit, problems arise, for example, a malfunction is caused by a clock skew during scan shifting, multi-phase clocks can not be handled, or a clock failure can not be detected.
In Japanese Patent Laid-Open No. 3-181098, a logic integrated circuit including flip-flop circuits where a problem of the clock skew on shifting is solved is disclosed. However, in such flip-flop circuits, as shown in FIG. 1, a clock signal CK and a second clock signal SCKO are applied in common to a plurality of flip-flop circuits 60, and thus there is restriction in design in that all the flip-flop circuit are necessarily operated by the same clock signal CK. Hence, multi-phase clocks cannot be handled.
In Japanese Patent Application No. 3-316692, another logic integrated circuit obtained by a scan design so as to solve the clock skew problem on shifting and to enable a handling of multi-phase clocks is disclosed.
In this logic integrated circuit, as shown in FIG. 2, two clock signals CK1 and CK2 and a first test clock signal SCK1 are selected by a test mode signal TS. That is, when no testing is carried out, the flip-flop circuits 60 are operated by two-phase clocks of the two clock signals CK1 and CK2, and, when a testing is carried out, the flip-flop circuits 60 are operated by the first test clock signal SCK1 and a second test clock signal SCK2.
However, in this circuit, the two clock signals CK1 and CK2 are not used at the testing, and hence the testing of the two clock signals CK1 and CK2 can not be performed. Further, in this logic integrated circuit, the used flip-flop circuits must be positive flip-flop circuits, which is restriction in design.
Generally, in logic integrated circuits, multi-phase clocking scheme is widely used. Thus, design for testability method is required to deal with such a logic integrated circuit, and all parts within a circuit should be testable.
However, in the conventional logic integrated circuit, as described above, when the normal clocks and the test clocks are used together, the multi-phase clocks can not be handled, and also, when the normal clocks are selected by the test mode signal, the normal clocks can not be tested.